The present invention relates to a nonvolatile semiconductor memory for reading out data by a read circuit using a flip-flop type sense amplifier and, more particularly, to a nonvolatile semiconductor memory demanded for a high-speed or low-voltage read or requiring address switching during precharge due to system limitations.
A conventional nonvolatile semiconductor memory such as an EPROM for reading out data by comparing changes in drain voltages (bit line voltages) of read (target) and reference cells by a precharge/discharge method using a flip-flop type sense amplifier will be described. This conventional nonvolatile semiconductor memory is disclosed in detail in Jpn. Pat. Appln. KOKOKU Publication No. 7-70235.
FIG. 1 is a circuit diagram showing a memory cell array in the conventional nonvolatile semiconductor memory.
In FIG. 1, data storage read cells are laid out in an array to form a read cell group 102 on a memory surface 100 of the nonvolatile semiconductor memory. In this read cell, the threshold voltage is set to turn on/off the cell in accordance with storage data upon selection. Reference cells are laid out in an array to form a reference cell group 104 on the memory surface 100. In this reference cell, the threshold voltage is set to turn on the cell upon selection. The read and reference cell groups 102 and 104 form a memory cell array.
In this memory cell array, a bit line 106 commonly connected to the drains of read and reference cells on the same column is connected to an I (Intrinsic) type transistor (to be referred to as an I-type Tr) 110 via a column select transistor (to be referred to as a column select Tr) 108. The I-type Tr has an intrinsic semiconductor in an active region.
In the memory cell array, the control gates of read cells on the same row are connected to a common word line 112a, whereas the control gates of reference cells are connected to a common word line 112b. In the memory cell array, a common source line 114 connected to the sources of the read and reference cells is connected to a reference potential (GND) via a discharge transistor (to be referred to as a discharge Tr) 116.
Similarly, data storage read cells are laid out in an array to form a read cell group 122 on a memory surface 120 of the nonvolatile semiconductor memory. In this read cell, the threshold voltage is set to turn on/off the cell in accordance with storage data upon selection. Reference cells are laid out in an array to form a reference cell group 124 on the memory surface 120. In this reference cell, the threshold voltage is set to turn on the cell upon selection. The read and reference cell groups 122 and 124 form a memory cell array.
In this memory cell array, a bit line 126 commonly connected to the drains of read and reference cells on the same column is connected to an I-type Tr 130 via a column select Tr 128. In the memory cell array, the control gates of read cells on the same row are connected to a common word line 132a, while the control gates of reference cells are connected to a common word line 132b. In the memory cell array, a common source line 134 connected to the sources of the read and reference cells is connected to the reference potential (GND) via a discharge Tr 136.
In the nonvolatile semiconductor memory shown in FIG. 1, in a read from, e.g., a read cell RD10 of the memory surface 100, a reference cell RF10 of the memory surface 120 is selected and used. The difference between the read and reference cells RD10 and RF10 is that the read cell RD10 is designed with a larger transconductance Gm.
When the read cell RD10 is an ON cell (in which no data is written), the memory surface 100 and memory surface 120 are set to completely the same precharge state (potentials of all the portions are equal) via precharge transistors (to be referred to as precharge Trs) 138 and 140. Upon discharge, the bit line potential (input potential to a flip-flop 142) on the read cell side (memory surface 10 side) first exceeds the circuit threshold of the flip-flop 142 owing to the difference in transconductance Gm to invert an output F/F-OUT1 of the flip flop 142 from "0" to "1".
When the read cell RD10 is an OFF cell (in which data is written), the bit line potential on the reference cell side (memory surface 40 side) which is always ON first exceeds the circuit threshold of the flip-flop 142 to invert an output F/F-OUT2 of the flip flop 142 from "0" to "1". Even if the bit line potential on the read cell side then exceeds the circuit threshold of the flip-flop 142 due to OFF leakage or the like, the output F/F-OUT1 is held at "0". In this way, in the conventional nonvolatile semiconductor memory, whether the read cell RD10 is an ON or OFF cell is read out depending on "1" or "0" of the output F/F-OUT1.
The conventional nonvolatile semiconductor memory operates normally as far as the read cell side surface and reference cell side surface are equal in precharge state as much as possible in a read from an ON cell. To operate the memory within the limitation, the read and reference cell sides have the same memory cell array arrangement, and the parasitic resistances and parasitic capacitances belonging to the read and reference cells RD10 and RF10 are made equal.
Considering entrance of charges to an adjacent cell commonly connected to the source line, a capacitance to be precharged changes depending on whether data is written in the adjacent cell.
FIG. 2 is an equivalent circuit diagram showing the parasitic capacitances of the bit and source lines of the memory cell array in the conventional nonvolatile semiconductor memory. Of memory cells commonly connected to the source line, only a memory cell connected to selected bit and word lines is an ON cell, and remaining memory cells are OFF cells. Since only the read cell RD10 is an ON cell on the read cell side, a parasitic capacitance Cread on the read cell side is given as follows. Since all the reference cells RF10 are ON cells on the reference cell side, a parasitic capacitance Cref on the reference cell side is given as follows.
Cread=C.sub.BD1 +C.sub.SD PA1 Cref=C.sub.BR1 +C.sub.SR +C.sub.BR2 +C.sub.BR3 +C.sub.BR4
where Cread&lt;Cref for C.sub.BD1 =C.sub.BR1 and C.sub.SD =C.sub.SR ; and C.sub.BD1, C.sub.BD2, C.sub.BD3, and C.sub.BD4 are parasitic capacitances by a read cell side bit line, C.sub.SD is a parasitic capacitance by a read cell side source line, C.sub.BR1, C.sub.BR2, C.sub.BR3, and C.sub.BR4 are parasitic capacitances by a reference cell side bit line, and C.sub.SR is a parasitic capacitance by a reference cell side source line.
If the precharge period is short in this state, charge share occurs. If charge share or the like makes the precharge states of the read and reference cell sides different from each other, the discharge speed is influenced by another factor except for the aforementioned transconductances Gm of the read and reference cells RD10 and RF10. In the worst case, as shown in FIG. 3, charge share causes a reverse phenomenon that the reference cell side is discharged prior to the read cell side, thus reading out data from an ON cell as an OFF cell.
To avoid this problem, the nonvolatile semiconductor memory adopts a read method of turning on the discharge transistor slightly before the completion of precharge and removing charges entering from the source line, or a method of keeping the discharge transistor on even during the precharge period to prevent entrance of charges to an adjacent cell. The latter method is employed when the priority is given to the speed rather than the current consumption.
In either method, however, charges may be unbalanced to cause malfunction if the bit line of the memory cell is not satisfactorily precharged. A sufficiently long precharge period must therefore be ensured.
For this reason, in the conventional nonvolatile semiconductor memory, an address setup period is set not to switch the address during the precharge period. FIG. 4 is a timing chart showing a read from an ON cell in the conventional nonvolatile semiconductor memory. As shown in FIG. 4, precharge starts after a predetermined address setup period upon reception of an address signal. This is because if the address is switched during the precharge period, an actual period for precharging a target bit line is shortened.
The length of the address setup period is determined by a delay time before an input address signal is decoded to select bit and word lines, and is substantially determined by the number of logic stages of a decoding circuit and the power supply voltage. In the nonvolatile semiconductor memory for a synchronous read, although the precharge period and the sense period by the flip-flop can be shortened, the total access time in a read cannot be shortened unless the address setup period is shortened or eliminated.
Recent nonvolatile semiconductor memories adopt interleaving or the like as a high-speed read method. In such a read, the system may not set any address setup period. In this case, the conventional read method described above cannot be used.